1. Field of the Invention
The present invention relates to a simulator for simulating the operation of elements included in a circuit to be simulated while verifying timing errors or test rule errors of the elements.
2. Description of the Background Art
Logic simulators have found wide usage as means for checking logic operations and timing verification in the design of logic circuits. There are simulators only for the timing verification.
FIG. 22 is a flow chart of the timing verification of a conventional simulator. The operation will be described hereinafter with reference to FIG. 22.
In the step S1, an input test pattern signal is inputted to an input terminal of a circuit to be simulated. The outputs of respective elements included in the circuit are calculated, whereby the circuit is simulated. In the step S2, timing errors in the input and output signals of the elements are verified as a function of the simulation results provided in the step S1.
When the timing error is detected in the step S3, the process proceeds to the step S4. In the step S4, an error message list is outputted which is helpful for investigation of causes for the timing error. The error message list includes, for example, the type of timing error, the time at which the error has been caused, the element in which the error has been caused, and the like. When no timing error is detected in the step S3, the process does not proceed to the step S4 but to the step S5.
In the step S5, it is checked whether or not the simulation is completed for all of the elements included in the circuit to be simulated. If an unsimulated element is found, the process returns to the step S1. The operation of the steps S1 to S5 is repeated until the simulation is completed for all of the elements.
The simulator thus executes the timing verification.
The logic simulators are used in a few cases as means for checking logic operations and test rule verification in the design of the logic circuits. The test rule verification is minimized, if executed.
FIG. 23 is a flow chart of the test rule verification of the conventional simulator. The operation will be described below with reference to FIG. 23.
Initially, the input test pattern signal is inputted to the input terminal of the circuit to be simulated in the step S6. The outputs of the respective elements are calculated, whereby the circuit is simulated.
In the step S7, it is checked whether or not the simulation is completed for all of the elements included in the circuit. When an unsimulated element is found, the process returns to the step S6. The operation of the steps S6 and S7 is repeated until the simulation is completed for all of the elements.
When the simulation is completed, test rule errors in the output (and input) signals of the elements are verified in the step S8.
When the test rule error is detected in the step S9, the process proceeds to the step S10. An error message list is outputted in the step S10, which includes the type of test rule error, the element in which the error has been caused, and the like. When no test rule error is detected in the step S9, no error message is outputted and the process is terminated.
The simulator thus executes the test rule verification.
The conventional simulator verifies the timing errors or test rule errors of the elements in the above-mentioned manner to output the timing error message or test rule error message.
The verification contents of the timing errors are however fixed. Only specified timing errors are verified for any element. For example, only a set-up timing error, a spike error and a hazard error are verified where the element is a flip-flop. Check values as an error condition parameter of various types of timing errors are also fixed. There has been a problem that the timing errors of the same type are not verified with different check values.
Similarly, the verification contents of the test rule errors are fixed. Only specified test rule errors are verified (e.g., an Icc leak error, a DC test error, a bus conflict error, and an output buffer simultaneous change number check error). Check values as an error condition parameter of various types of test rule errors are also fixed. There has been a problem that the test rule errors of the same type are not verified with different check values.